A power semiconductor module has a problem in suppressing a surge voltage that is generated when a semiconductor switching element is switched. Therefore, it is necessary to reduce the wiring inductance.
For example, Japanese Patent Laying-Open No. 2005-216876 (Patent Document 1) relates to a power semiconductor module configuring upper and lower arms of one phase by connecting in series two of a group of elements for one arm, each group formed of an IGBT (Insulated Gate Bipolar Transistor) chip and a diode chip connected antiparallel to the IGBT. The input/output terminal of the IGBT is connected to positive side DC power supply terminal, a negative side DC power supply terminal, and a load side output terminal via a copper foil pattern insulated from each other on an insulative substrate. The wire corresponding to the input/output current path of the upper arm side IGBT chip is arranged in proximity to the wire corresponding to the input/output current path of the lower arm side diode chip. Accordingly, the mutual inductance is increased, resulting in reduction in the wiring inductance.
According to Japanese Patent Laying-Open No. 2005-197433 (Patent Document 2), the positive side DC output conductor and the negative side DC output conductor are arranged at substantially the middle of the longer side direction on a rectangular insulation substrate. Further, a semiconductor element chip such as an IGBT and a diode chip are arranged at both sides so as to sandwich the conductors. Accordingly, the mutual inductance caused by the current flowing when the semiconductor element is switched is increased to reduce the total inductance value.